Nearly Exact Signal Probabilities for Synchronous Sequential Circuits { an Experimental Analysis

In this article we present a strategy how to estimate the signal probabilities for synchronous sequential circuits. For each line in the circuit an OBDDs is constructed only once. Using this OBDD the signal probabilities in every succeeding time frame is computed. We investigated a large set of the ISCAS'89 benchmark circuits, showing that the proposed strategy estimates 75% of all signals considered with a relative error of only 10% or less. The knowledge of signal probabilities and fault detection probabilities has been proven useful almost everywhere in the area of deterministic and random testing of combinational circuits. This knowledge is even more valuable for sequential circuits. For combinational circuits, highly eecient tools have been developed for that task. Some base on sophisticated approximation strategies 8, 11, 17], other compute the exact value 7, 10, 12]. An other important application of signal probabilities is switching activity analysis as shown e.g. in 16]. Even in the case of a combinational circuit, the exact algorithms have exponential time complexity measured in the number of inputs. So, we do not expect an eecient exact algorithm for all synchronous sequential circuits, but heuristics approximating the real value. Here, we consider an iterative network representation of the nite state machine, using the gate level realization. For that, we assume secondary inputs and secondary outputs representing the outputs and inputs of the memory elements. We compute an estimation of the signal probabilities of every lead (signal) in the circuit over a given number of time frames similar to a Markov-process. For this work, we also compute the real signal probabilities by symbolic methods, as far as possible. Thus, we can show the accuracy of the estimation by computing the relative error for each lead. To our knowledge, in literature no work has been presented, considering an estimation of the signal probability for each line in a sequential circuit over the progress of time. Only some